| Feature |
LRS-100 |
LRS-205 |
LRS-220 |
| Shift
Register |
| Maximum
Size |
Programmable
Feedback
Programmable Initial Fill
Programmable Length |
|
| - |
| 16-Stages
or Dual 8-Stages |
Yes
Yes
Yes |
|
|
| - |
| Dual
32-Stages |
Yes
Yes
Yes |
|
| Modulation
Codes |
BPSK
QPSK
OQPSK (SQPSK) |
Gold/JPL
Dual QPSK (aka Gold QPSK)
Dual OQPSK (aka Gold
OQPSK) |
Syncopated
Frequency Hopping |
|
| - |
Yes
Yes
No |
Yes
(8-stages max.)
Yes (8-stages max.)
Yes (8-stages max.) |
Yes
(8-stages max.)
Yes |
|
| - |
Yes
Yes
Yes |
No
No
No |
No
Yes |
|
| - |
Yes
Yes
Yes |
Yes
Yes
Yes |
Yes
Yes |
|
| Clock |
| Maximum
Rate |
Internal
Source
External Input |
|
| - |
| 25
MHz |
Yes,
1-2-5 Sequence
Yes |
|
| - |
| 25
MHz |
No
(future upgrade)
Yes |
|
| - |
| 25
MHz |
No
(future upgrade)
Yes |
|
| Data |
| Maximum
Rate |
Internal
Simulator
External Input |
|
|
| - |
| 25
MHz |
No
(future upgrade)
Yes |
|
| - |
| 25
MHz |
No
(future upgrade)
Yes |
|
| Special
Modes |
Burst
(for radar applications)
Master/Slave
| |
(for
synchronizing two
generators) |
|
|
|
|
|
| Inputs |
| Level
(logic family) |
External
Clock
External Data |
High-Speed
Controls
| |
(for
starting, stopping, and
presetting the shift
register) |
|
|
|
|
|
| Outputs |
| Level
(logic family) |
Direct
Sequence
Parallel (for frequency
hopping) |
Clock
Strobe (epoch) |
Data
Simulator Outputs:
| |
Data
Clock
Strobe (epoch) |
|
|
|
| - |
| TTL |
Yes
Yes |
Yes
(buffered Clk In)
Yes |
| - |
|
| - |
| TTL |
Yes
Yes |
Yes
(buffered Clk In)
Yes |
| - |
|
| Options |
| GPIB
(IEEE 488.2, SCPI) |
Custom
Configurations
Upgradable |
|
|
| - |
| $2,000
($2,200 Int'l) |
Yes
Yes |
|
| - |
| $2,000
($2,200 Int'l) |
Yes
Yes |
|
|
|
|
|
|
| Price
(US $) |
Domestic
(USA & Canada)
International |
|
|
|
|
